1. Technical Field of the Invention
The present invention relates generally to semiconductor memories, and more particularly, to a row and column accessible memory circuit with a built-in multiplex.
2. Description of Related Art
Memory circuits organized as an array of rows and columns are typically accessed by using what is known as a row access operation. Essentially, a row address is supplied to the memory circuit and, based on the address information, a particular row or wordline is driven high. Depending on whether a read cycle or write cycle is involved, input data provided via an input/output (I/O) block is stored at the memory locations disposed on the selected row or the data stored thereat is read therefrom.
Row accessible memory such as set forth above is well known in the memory design art and is advantageous in many applications. However, there are certain situations where the conventional row accessible memory solutions are less than satisfactory. For example, if the memory locations comprising a particular column or bitline are to be accessed, the array needs to be accessed a number of times on per row basis depending upon the number of memory cells in the bitline. For arrays of even modest size, such a requirement can pose a significant limitation in terms of additional access cycles, thereby compromising the memory circuit""s performance.
Column accessible memory solutions are available for applications requiring special functionality such as memory access on a per column basis. Although the conventional column accessible memory circuits are an improvement over the row accessible memories, several shortcomings and deficiencies remain. First, a separate I/O block is typically required for effectuating column access operations. When a column address is provided, a control signal operable with a logic block is utilized to generate a select signal for a particular column. The read/write bitlines associated with the selected column are coupled to a column I/O block that is different from the row I/O block used for the typical row access operations. Moreover, because common data-in and dataout lines are employed for the row and column access operations (in order to minimize the I/O bus), an external multiplexer circuit is required to select between the data paths operable with the row accesses and the data paths operable with the column accesses. It should be appreciated, accordingly, that the conventional column accessible memories require expensive additional silicon area for the extra circuitry. Furthermore, because of the layout considerations arising out of the extra blocks, routing issues become prominent as well.
Based on the foregoing, it should be apparent to those skilled in the art that there has arisen an acute need for an effective and efficient memory solution (especially for applications requiring special functionality, for example, telecommunications network elements such as routers, switches, and the like) that allows both row and column access operations while improving performance and silicon area utilization.
Accordingly, the present invention is directed to a row and column accessible memory having a plurality of memory cells organized as an array of N rows and N columns, wherein the column accessible functionality is achieved without separate column I/O block circuitry, multiplexer circuitry and associated metal routing.
A control logic block and decoder block are operable to effectuate either a row access operation for accessing a selected row or a column access operation for accessing a selected column based on a plurality of address signals supplied to the memory. Each memory cell is provided with a first pair of read and write ports for effectuating the row access operations (controlled through a pair of row read wordline select and row write wordline select signals, respectively) and a second pair of read and write ports for effectuating the column access operation (controlled through a pair of column read wordline select and column write wordline select signals, respectively). A single I/O block is utilized for sensing and data I/O operations in the row and column access modes because the row read bitlines (i.e., the row read ports) are coupled to the column read bitlines (i.e., the column read ports) and the row write bitlines (i.e., the row write ports) are coupled to the column write bitlines (i.e., the column write ports) in the memory cells placed in one of the two diagonals of the array.
When a row address is provided, row access control signals (i.e., row read wordline select and row write wordline select signals) are generated, which effectuate the row access operation with respect to a particular row based on the supplied address. That is, in the row access operation, the memory circuit behaves like a conventional row accessible memory. When a column address is supplied, only column access control signals (i.e., column read wordline select and column write wordline select signals) are generated. Since the column read bitlines and row read bitlines are commonly coupled in the diagonal cells (hereinafter referred to as the xe2x80x9cprogrammedxe2x80x9d cells (P-cells) or xe2x80x9cspecial memory cellsxe2x80x9d), the memory cells in the accessed column generate data on the row read bitlines corresponding to the diagonal cells, similar to a conventional row access operation.
In another aspect, the present invention is directed to a special memory cell (i.e., P-cell) structure for use in a row and column accessible memory device, wherein a plurality of such P-cells form a diagonal portion of an array associated with the memory device. Each P-cell comprises a first pair of read and write ports operable with respect to a row access operation and a second pair of read and write ports operable with respect to a column access operation in response to an access control signal. A pair of inverters are coupled to each other to form a first data node and a second data node for storing complementary binary data thereat in the P-cell. A row write transistor is coupled to the first data node wherein the row write transistor is operable to provide a data value available at the first write port to the first data node when activated by a row write wordline select signal generated by a decoder circuit. A row read transistor is coupled to the second data node wherein the row read transistor is operable to provide a data value available at the second data node to the first read port when activated by a row read wordline select signal generated by the decoder circuit.
To effectuate column access operations, a column write transistor is coupled to the first data node wherein the column write transistor is operable to provide a data value available at the second write port to the first data node when activated by a column write wordline select signal generated by the decoder circuit of the row and column accessible memory device. In similar manner, a column read transistor is coupled to the second data node wherein the column read transistor is operable to provide a data value available at the second data node to the second read port when activated by a column read wordline select signal generated by the decoder circuit. Further, for each P-cell placed in one of the two diagonal portions of the array, the first and second write ports are tied together at a common write node and the first and second read ports are tied together at a common read node. This arrangement allows the use of a single I/O block for both row and column access operations.
In a further aspect, the present invention is directed to a memory read operation in a row and column accessible memory array organized as N rows by N columns. A clock signal and an access control signal are asserted to initiate a memory read cycle in a row access operation or a column access operation based on a plurality of address signals supplied to a control block coupled to the memory array. If the row access operation is specified, a row read wordline select signal is generated for a selected row of the memory array. Thereafter, a data voltage is developed as a row read bitline signal associated with a particular memory cell disposed on the selected row in response to the row read wordline select signal. Data on the row read bitline signal is sensed in an I/O block coupled to the memory array, which is then read on an appropriate data output line associated with the I/O block.
If the column access operation is specified, a column read wordline select signal is generated for a selected column of the memory array. A column read bitline signal is then developed for a particular memory cell disposed on the selected column in response to the column read wordline select signal. Data on the column read bitline signal is sensed in the I/O block for outputting the data on an appropriate data output line associated therewith.
In a still further aspect, the present invention is directed to a memory write operation in a row and column accessible memory array organized as N rows by N columns. Similar to the memory read operation summarized above, a clock signal and an access control signal are asserted to initiate a memory write cycle in one of a row access operation and a column access operation based on a plurality of address signals supplied to a control block coupled to the memory array. If the row access operation is specified, a row write wordline select signal is generated for a selected row of the memory array. A row write bitline signal is generated for a particular memory cell disposed on the selected row in response to a data value available via a data input line through an I/O block of the memory array. The data value associated with the row write bitline signal is then stored at a data node in the particular memory cell. If the column access operation is specified, a column write wordline select signal is generated for a selected column of the memory array. Thereafter, a data value available via a data input line through the I/O block is transferred to a column write bitline signal associated with a particular memory cell. Subsequently, the data value on the column write bitline signal is stored at a data node in the particular memory cell in the selected column.